Project Experience

Some examples of the projects that Interconnect Engineering has experience with are:

• 100Gbit/s interface designs (Multiple concatenated 11.5Gbit/s links).
  
  
• 1-11.5Gbit/s Xilinx Rocket I/O and Altera Stratix GX link interface designs.
  
  
• 1-12.5Gbit/s Backplane/Midplane designs.
  
  
• Many XAUI/RXAUI based (3.125Gbit/s/6.25Gbit/s) designs as well as Interlaken (6.4Gbit/s) and PCIe 1.0/2.0 designs.
  
  
• OC-192 (10Gbit/s) transponder layout and simulation experience.
  
  
• Optical front-end design from 155.52Mbit/s to 10.3125Gbit/s.
  
  
• 3.125Gbit/s Agilent DWDM transceiver design experience.
  
  
• POSPHY Level 3/4, SPI-4.1/4.2/5, TFI-5 and OIF type interface experience.
  
  
• Multi-vendor, high band-width, Network Processor designs.
  
  
• Multiple-load DDR1/2/3 and SDR SDRAM, QDR SRAM, SyncSRAM, SIO, CIO, FCRAM and RLDRAM Interfaces.
  
  
• Multiple SIMM/DIMM memory interfaces (DDRX up to 1333Mbit/s).
  
  
• Board level clock distribution analysis (duty cycle distortion, jitter, skew, trace delay, input loading).
  
  
• Very familiar with all termination types for resolution of transmission line effects for reliable system performance and EMI reduction for all common routing topologies (point-to-point, star, multi-drop bus, V, T, ring, daisy chain, "hairball", etc.).
  
  
• Very familiar with I/O technologies such as SSTL1.5/1.8/2/3, CML, LVDS, HSTL18, HSTL15, LVTTL, LVCMOS25, LVCMOS18, GTL/+, NTL, etc.
  
  
• I/O buffer selection to obtain superb signal integrity and low EMI.
  
  
• Power Distribution System analysis to ensure robust, low noise power delivery to all devices.
  
  
• Timing analysis and design to ensure margin over process, voltage and temperature.